The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure including at least one high k/metal gate transistor having a low resistive source region and drain region and a method of fabricating the same.
In the semiconductor industry, a gate stack including a high k gate dielectric (a gate dielectric having a dielectric constant of greater than 4.0, typically greater than 7.0) and a metal gate is one of the most promising options for continuing complementary metal oxide semiconductor (CMOS) scaling.
One of the process schemes for fabricating a high k/metal gate metal oxide semiconductor field effect transistor (MOSFET) is a replacement gate process. In a replacement gate process, a MOSFET can be fabricated using a sacrificial gate electrode. In such a process, the sacrificial gate electrode is formed first, then a source region and a drain region are formed at the footprint of the sacrificial gate electrode, and thereafter the sacrificial gate electrode is replaced by a gate stack including a high k gate dielectric and a metal gate. Since the gate stack including the high k gate dielectric and the metal gate is formed after high temperature processing steps, the replacement gate process has the advantage of minimal damage on the high k gate dielectric and the metal gate. Moreover, a wide range of metals can be selected for the gate conductor.
Continuous scaling of MOSFET devices requires very sharp source junctions and drain junctions. In conventional MOSFET processing, including the replacement gate processing scheme mentioned above, the source region and the drain region of the MOSFETs are formed by ion implantation, followed by an activation anneal. Such processing however leads to diffused source junctions and drain junctions which, in turn, degrade short-channel control. Also, the diffused source junctions and drain junctions increase the resistance of the source region and the drain region, respectively, and hence reduce device performance.
Furthermore, pitch scaling introduces challenges in block level patterning. Resist residues at tight pitches necessitate high energy source and drain implants which worsen the two issues mentioned above.